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Vhdl Signal Assignment Delay

I am trying to understand how assignments with 'after foo' work, so I read about the delay model and simulated the following code:

In Xilinx's Vivaldo, I get the following output:

When what I expected was simply a 10ns delay. Can someone explain what is going on here?


EDIT: To be clear, my beef here is that, if the behaviour I'm describing is indeed default, it sounds like an awful leak of abstraction: when I write

the behavior I expect would be one that simulates a latch being driven (temp is the input, goes_out is the output), and so temp would have to keep its new value for 10ns in order to properly drive the latch (hence the "inertial delay" model).

Now, if this were indeed the case, the proper behaviour for my circuit would be to do nothing, since I attempt to write a 'Z' to goes_out and immediately after that, that 'Z' is overwritten by a '1' - therefore, the value of temp driving the latch is not kept, and it fails to drive goes_out. (obviously you can't drive latches with 'Z', thought I could use '0' and '1' and my point would stand)

So my question is: is there a good reason for this odd behaviour? To me, it seems trivial to "make things right": the algorithm that simulates the inertial delay could check for changes in the value of temp in the delta cycle it is being assigned to goes_out, and cancel the assignment if something is happening - instead of only cancelling the assignment if the NEW value of temp does not change.

vhdlsimulationdelay

Signal Assignment

Formal Definition

A signal assignment statement modifies the projected output waveforms contained in the drivers of one or more signals

Simplified Syntax

signal_name <= [delay_mechanism ] waveform ;

signal_name <= [delay_mechanism ] waveform1 when condition1 else

      [delay_mechanism ] waveform2 when condition2 else

       . . .

      [delay_mechanism ] waveformn;

with selection select

    signal_name <= [delay_mechanism ] waveform1 when choice1,

      [delay_mechanism ] waveform2 when choice2,

      . . .

      [delay_mechanism ] waveformn when others;

Description

Signal assignment statement can appear inside a process or directly in an architecture. Accordingly, sequential signal assignment statements and concurrent signal assignment statements can be distinguished. The latter can be divided into simple concurrent signal assignment, conditional signal assignment and selected signal assignment.

The target signal can be either a name (simple, selected, indexed, or slice) or an aggregate.

All signal assignments can be delayed. See delay for details.

Sequential signal assignment

If a sequential signal assignment appears inside a process, it takes effect when the process suspends. If there are more than one assignments to the same signal in a process before suspension, then only the last one is valid. Regardless of the number of assignments to a signal in a process, there is always only one driver for each signal in a process (Example 1).

If a signal is assigned a value in a process and the signal is on the sensitivity list of this process, then a change of the value of this signal may cause reactivation of the process (Example 2).

Concurrent signal assignment

The concurrent signal assignment statements can appear inside an architecture. Concurrent signal assignments are activated whenever any of the signals in the associated waveforms change their value. Activation of a concurrent signal assignment is independent from other statements in given architecture and is performed concurrently to other active statements (Example 3). If there are multiple assignments to the same signal then multiple drivers will be created for it. In such a case, the type of the signal must be of the resolved type (see resolution function).

Conditional signal assignment

Conditional signal assignment is a form of a concurrent signal assignment and plays the same role in architecture as the if then else construct inside processes. A signal is assigned a waveform if the Boolean condition supported after the when keyword is met. Otherwise, the next condition after the else clause is checked, etc. Conditions may overlap.

A conditional signal assignment must end with an unconditional else expression (Example 4).

Selected signal assignment

Selected signal assignment is a concurrent equivalent of a sequential case construct. All choices for the expression must be included, unless the others clause is used as the last choice (Example 5). Ranges and selections can be used as the choice (Example 6). It is not allowed for choices to overlap.

Examples:

Example 1

signal A, B, C, X, Y, Z : integer;
process (A, B, C)
begin
  X <= A + 1;
  Y <= A * B;
  Z <= C - X;
  Y <= B;
endprocess;

 
When this process is executed, signal assignment statements are performed sequentially, but the second assignment (Y <= A * B) will never be executed because only the last assignment to Y will be activated. Moreover, in the assignment to Z only the previous value of X will be used as the A + 1 assignment will take place when the process suspends.

Example 2

signal A, B, C, X, Y, Z : integer;
process (A, B, C)
begin
  X <= A + 1;
  Y <= A * B;
  Z <= C - X;
  B <= Z * C;
endprocess;

 
When the process is activated by an event on the signal C this will cause change on the signal B inside a process, which will in turn reactivate the process because B is in its sensitivity list.

Example 3

architecture Concurrent of HalfAdder is
begin
  Sum <= A xor B;
  Carry <= A and B;
endarchitecture Concurrent;

 
The above architecture specifies a half adder. Whenever A or B changes its value, both signal assignments will be activated concurrently and new values will be assigned to Sum and Carry.

Example 4

architecture Conditional of TriStateBuffer is
begin
  BufOut <= BufIn when Enable = '1'
    else 'Z';
endarchitecture Conditional;

 
The architecture specifies a tri-state buffer. The buffer output BufOut will be assigned the value of buffer input BufIn only when the Enable input is active high. In all other cases the output will be assigned high impedance state.

Example 5

architecture Concurrent of UniversalGate is
begin
  with Command select
     DataOut <= InA and InB when "000",
                InA or InB when "001",
                InA nand InB when "010",
                InA nor InB when "011",
                InA xor InB when "100",
                InA xnor InB when "101",
                'Z' whenothers;
endarchitecture Concurrent;

 
Architecture of UniversalGate is specified with a selected signal assignment. Depending on the value of the Command signal, the DataOut signal will be assigned value resulting from the logical operation of two inputs. If none of the specified codes appears, the output is set to high impedance.

Example 6

with IntCommand select
  MuxOut <= InA when 0 | 1,
            InB when 2 to 5,
            InC when 6,
            InD when 7,
            'Z' whenothers;

 
A specialized multiplexer is defined here with a selected signal assignment. Note that both range and selections can be used as a choice.

Important Notes

  • Signal assignment statements are generally synthesizeable but delays are usually ignored.

  • Choices in selected signal assignment are separated by colons.

  • All signal assignments can be labeled for improved readability.

 

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