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Vhdl Variable Assignment Statement

Variable Assignment

Formal Definition

A variable assignment statement replaces the current value of a variable with a new value specified by an expression.

Simplified Syntax

variable_name := expression ;


The variable assignment statement modifies the value of the variable. The new value of the variable is obtained by assigning an expression to this variable. In order to distinguish variable assignment from signal assignment, the variable assignment symbol is different (:=).

The expression assigned to a variable must give results of the same type as the variable. The target at the left-hand side of the assignment can be either a name of a variable or an aggregate.

In the first case, the target can be in the form of simple name, selected name, indexed name or slice name (Example 1).

In case of aggregate as the target of the assignment, the type of the aggregate must be determinable from the context, including the fact that the type must be of the composite type. Each element of the aggregate must be in the form of the locally static name, which represents variable (Example 2).

The element association of aggregate, similarly to names, may have forms that are more complex: selected name, indexed name or slice name (Example 3).


Example 1

variable X, Y : REAL;
variable A, B : BIT_VECTOR (0 to 7);
type BIT_RECORD isrecord
  bitfield : BIT;
  intfield : Integer;
variable C, D : BIT_RECORD;
X := 1000.0;
A := B;
A := "11111111";
A (3 to 6) := ('1','1','1','1');
A (0 to 5) := B (2 to 7);
A (7) := '0';
B (0) := A (6);
C.bitfield := '1';
D.intfield := C.intfield;

The above examples of variable assignments are grouped in the following way: after the declarations the first group is a group of assignments with simple names as targets, then slice names, indexed names and finally selected names.

Example 2

variable E : BIT;
variable I : INTEGER;
(E, I) := C;

The aggregate used above as a target for a variable assignment could be used for the variable C declared in such a way as in the Example 1. E will be assigned the value of C.bitfield and I - C.intfield.

Example 3

type BIT_VECTOR_RECORD isrecord
  a: BIT_VECTOR(0 to 7);
  b: Integer;
variable G, H : BIT_VECTOR_RECORD;
(C.bitfield, C.intfield) := D; -- aggregate with selected name
(G.a(0 to 7), K) := H; -- aggregate with sliced name
(G.a(0), K) := D; -- aggregate with indexed name

Aggregates can use different forms of names.

Important Notes

  • Variable assignment can be labeled.

  • Variable assignment takes effect immediately.

  • Variable assignment can not be specified with a delay.


|Summary |Design Units |Sequential Statements |Concurrent Statements |Predefined Types |Declarations |

|Resolution and Signatures |Reserved Words |Operators |Predefined Attributes |Standard Packages |

VHDL Declaration Statements

Various declarations may be used in various design units. Check the particular design unit for applicability.

Declaration Statements

incomplete type declaration

Declare an identifier to be a type. The full type definition must be provided within this scope. type identifier ; type node ;

scalar type declaration

Declare a type that may be used to create scalar objects. type identifier is scalar_type_definition ; type my_small isrange -5 to 5 ; type my_bits isrange 31 downto 0 ; type my_float isrange 1.0 to 1.0E6 ;

composite type declaration

Declare a type for creating array, record or unit objects. type identifier is composite_type_definition ; type word isarray (0 to 31) of bit; type data isarray (7 downto 0) of word; type mem isarray (natural range <>) of word; type matrix isarray (integer range <>, integer range <>) of real; type stuff isrecord I : integer; X : real; day : integer range 1 to 31; name : string(1 to 48); prob : matrix(1 to 3, 1 to 3); endrecord; type node is -- binary tree record key : string(1 to 3); data : integer; left : node_ptr; right : node_ptr; color : color_type; endrecord; type distance isrange 0 to 1E16 units Ang; -- angstrom nm = 10 Ang; -- nanometer um = 1000 nm; -- micrometer (micron) mm = 1000 um; -- millimeter cm = 10 mm; -- centimeter dm = 100 mm; -- decameter m = 1000 mm; -- meter km = 1000 m; -- kilometer mil = 254000 Ang; -- mil (1/1000 inch) inch = 1000 mil; -- inch ft = 12 inch; -- foot yd = 3 ft; -- yard fthn = 6 ft; -- fathom frlg = 660 ft; -- furlong mi = 5280 ft; -- mile lg = 3 mi; -- league endunits;

access type declaration

Declare a type for creating access objects, pointers. An object of an access type must be of class variable. An object type identifier isaccess subtype_indication; type node_ptr isaccess node; variable root : node_ptr := new node'("xyz", 0, null, null, red); variable item : node := root.all;

file type declaration

Declare a type for creating file handles. type identifier isfileof type_mark ; type my_text isfileof string ; type word_file isfileof word ; file output : my_text; file_open(output, "my.txt", write_mode); write(output, "some text"&lf); file_close(output); file test_data : word_file; file_open(test_data, "test1.dat", read_mode); read(test_data, word_value);

subtype declaration

Declare a type that is a subtype of an existing type. Note that type creates a new type while subtype creates a type that is a constraint of an existing type. subtype identifier is subtype_indication ; subtype name_type is string(1 to 20) ; variable a_name : name_type := "Doe, John "; subtype small_int is integer range 0 to 10 ; variable little : small_int := 4; subtype word is std_logic_vector(31 downto 0) ; signal my_word : word := x"FFFFFFFC";

constant, object declaration

Used to have an identifier name for a constant value. The value can not be changed by any executable code. constant identifier : subtype_indication := constant_expression; constant Pi : real := 3.14159; constant Half_Pi : real := Pi/2.0; constant cycle_time : time := 2 ns; constant N, N5 : integer := 5; A deferred constant has no := constant_expression can only be used in a package declaration and a value must appear in the package body.

signal, object declaration

Used to define an identifier as a signal object. No explicit initialization of an object of type T causes the default initialization at time zero to be the value of T'left signal identifier : subtype_indication [ signal_kind ] [ := expression ]; signal a_bit : bit := '0'; a_bit <= b_bit xor '1'; -- concurrent assignment signal my_word : word := X"01234567"; my_word <= X"FFFFFFFF"; -- concurrent assignment signal foo : word register; -- guarded signal signal bar : word bus; -- guarded signal signal join : word wired_or; -- wired_or must be a resolution function signal_kind may be register or bus. A simple signal of an unresolved type can have only one driver. Note that "bit" is an unresolved type as is "std_ulogic", but, "std_logic" is a resolved type and allows multiple drivers of a simple signal.

variable, object declaration

Used to define an identifier as a variable object. No explicit initialization of an object of type T causes the default initialization at time zero to be the value of T'left variable identifier : subtype_indication [ := expression ]; variable count : integer := 0; count := count + 1; A variable may be declared as shared and used by more than one process, with the restriction that only one process may access the variable in a single simulation cycle. shared variable identifier : subtype_indication [ := expression ]; shared variable status : status_type := stop; status := start; Note: Variables declared in subprograms and processes must not be declared shared. Variables declared in entities, architectures, packages and blocks must be declared shared. Some analysers/compilers may require shared variables to be 'protected'. Note: Both signal and variable use := for initialization. signal uses <= for concurrent assignment variable uses := for sequential assignment

file, object declaration

Used to define an identifier as a file object. file identifier : subtype_indication [ file_open_information ] file_open_information [ open file_open_kind ] is file_logical_name file_open_kind from use STD.textio.all read_mode write_mode append_mode use STD.textio.all; -- declares types 'text' and 'line' file my_file : text open write_mode is "file5.dat"; variable my_line : line; write(my_line, string'("Hello."); -- build a line writeline(my_file, my_line); -- write the line to a file Note: The file_logical_name is a string in quotes and its syntax must conform to the operating system where the VHDL will be simulated. The old DOS 8.3 format in lower case works on almost all operating systems.

alias declarations

Used to declare an additional name for an existing name. alias new_name is existing_name_of_same_type ; alias new_name [ : subtype_indication ] : is [ signature ]; new_name may be an indentifier, a character literal or operator symbol alias rs is my_reset_signal ; -- bad use of alias alias mantissa:std_logic_vector(23 downto 0) is my_real(8 to 31); alias exponent is my_real(0 to 7); alias "<" is my_compare [ my_type, my_type, return boolean ] ; alias 'H' is STD.standard.bit.'1' [ return bit ] ;

attribute declaration

Users may define attributes to be used in a local scope. Predefined attributes are in the Predefined Attributes sectionattribute identifier : type_mark ; attribute enum_encoding : string; -- user defined type my_state is (start, stop, ready, off, warmup); attribute enum_encoding of my_state : typeis "001 010 011 100 111"; signal my_status : my_state := off; -- value "100"

attribute specification

Used to associate expressions with attributes. Predefined attributes are in the Predefined Attributes sectionattribute identifier of name : entity_class is expression ; entity_class architecturecomponentconfigurationconstantentityfilefunctiongrouplabelliteralpackageproceduresignalsubtypetypevariableunitsattribute enum_encoding : string; type my_state is (start, stop, ready, off, warmup); attribute enum_encoding of my_state : typeis "001 010 011 100 111"; signal my_status : my_state := off; -- value "100"

component declaration

Used to define a component interface. Typically placed in an architecture or package declaration. The component or instances of the component are related to a design entity in a library in a configuration. component component_name isgeneric ( generic_variable_declarations ) ; -- optional port ( input_and_output_variable_declarations ) ; endcomponent component_name ; generic_variable_declarations are of the form: variable_name : variable_type := value ; input_and_output_variable_declaration are of the form: variable_name : port_mode variable_type ; port_mode may be inoutinoutbufferlinkagecomponent reg32 isgeneric ( setup_time : time := 50 ps; pulse_width : time := 100 ps ); port ( input : in std_logic_vector(31 downto 0); output: out std_logic_vector(31 downto 0); Load : in std_logic_vector; Clk : in std_logic_vector ); endcomponent reg32; Then an instantiation of the reg32 component in an architecture might be: RegA : reg32 genericmap ( setup_time => global_setup, pulse_width => 150 ps) -- no semicolon portmap ( input => Ainput, output => Aoutput, Load => Aload, Clk => Clk ); An alternative to the component declaration and corresponding component instantiation above is to use a design entity instantiation. RegA : entity WORK.reg32(behavior) -- library.entity(architecture) genericmap ( global_setup, 150 ps) -- no semicolon portmap ( Ainput, Aoutput, Aload, Clk ); There is no requirement that the component name be the same as the design entity name that the component represents. Yet, the component name and design entity name are often the same because some systems automatically take the most recently compiled architecture of a library entity with the same name as the component name.

group template declaration

A group template declaration declares a group template, which defines the allowable classes of named entities that can appear in a group. group identifier is ( entity_class_list ) ; entity_class_list entity_class [, entity_class ] [ <> ] entity_class architecturecomponentconfigurationconstantentityfilefunctiongrouplabelliteralpackageproceduresignalsubtypetypevariableunits -- a group of any number of labels group my_stuff is ( label <> ) ;

group declaration

A group declaration declares a group, a named collection of named entities. group identifier : group_template_name ( group_member [, group member] ) ; group my_group : my_stuff ( lab1, lab2, lab3 ) ;

disconnect specification

A disconnect specification applies to a null transaction such as a guard becoming false. disconnect signal_name : type_mark after time_expression ; disconnectothers : type_mark after time_expression ; disconnectall : type_mark after time_expression ; disconnect my_sig : std_logic after 3 ns;

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